EN IEC 63093-2 pdf free download
EN IEC 63093-2 pdf free download.Ferrite cores – Guidelines on dimensions and the limits of surface irregularities – Part 2: Pot-cores for use in telecommunications, power supply, and filter applications.
4 Primary dimensions
4.1 Dimensions of pot-cores
4.1.1 General
Compliance with the following requirements ensures mechanical interchangeability of complete assemblies and wound coil formers.
4.1.2 Principal dimensions
The principal dimensions of pot-cores shall be as given in Table 1, Figure 1 and Figure 2. The dimensions of the cores may be checked by means of gauges. By way of example, a possible standard for these gauges is given in Annex B. In order to facilitate production it can be necessary to use gauges having dimensions differing from those given in Annex B, although no relaxation of the requirements for the dimensions of the cores given in Table 1 and in Table 2 is permitted.
5.4 Cracks
A single continuous crack which intersects the perimeter of the relevant surface at two points is not acceptable (see S1, S1′ and S1″ irregularities in Figure 6). The limits for cracks at various locations shown in Figure 6 and Figure 7 are given in Table 8.
5.5 Pull-out, crystallite and pore locations
Figure 8 shows examples of the locations of a pull-out, crystallite and pore on a pot core:
— the cumulative area of pull-outs on the bottom surface of the core shall be less than 25 % of the total respective surface area (including wire-way areas for the bottom surface);
— the single area of the crystallite located on any surface shall be less than 2 % of the respective surface area;
— the cumulative area of the crystallites located on any surface shall be less than 4 % of the respective surface area;
— the number of pores located on the same surface shall not exceed two; the total number of pores located on all surfaces shall not exceed five;
— a hole with an area larger than 1 mm2 on any surface is not acceptable.
5.3 Chips and ragged edges
5.3.1 General
The minimum area is taken as 0,5 mm2, to be distinguishable to the naked eye.
5.3.2 Chips and ragged edges on the mating surfaces
The areas of the chips located on the mating surfaces (Chip 1 and Chip 1’ irregularities in Figure 5) shall not exceed the following limits:
— the cumulative area of the chips shall be less than 4 % of the total mating surface (whether gapped or ungapped);
— the total length of the ragged edges shall be less than 25 % of the perimeter of the relevant mating surface.
5.3.3 Chips and ragged edges on the other surfaces
The allowable areas of chips on the other surfaces are doubled as compared to the limits for
the mating surface (see Figure 5, Chip 1”).
The rule for ragged edges is the same as that for the mating surface.
Chips and ragged edges are not acceptable on the inner edges of the wire slot area.
EN IEC 63093-2 pdf download.
